At present, the highest performing digital communications systems are based on systems in which data to be transmitted is protected by very high performance channel coding and is decoded iteratively by a weighted output decoder. Channel coding or error corrector coding improves transmission quality by inserting redundant bits into the message to be transmitted in accordance with a given law.
In the field of digital transmission, and especially when the transmission channel is a radio channel, the principal function of these corrector codes is to eliminate ambiguities in the transmitted message caused by the transmission channel. The channel decoder, which knows the coding law used on transmission, verifies if that law is still complied with on reception. If not, it detects that transmission errors are present.
The performance improvement achieved by these codes can be used to reduce the power consumption of terminals or to increase the volume of information transmitted.
Recently, considerable research has been conducted into channel coding using LDPC (low density parity check) error corrector codes.
These codes are now being promulgated by standardization bodies, for example, in the context of standardizing the IEEE 802.11n communications protocol intended for future wireless access networks (WLAN) operating at very high bit rates and the IEEE 802.16e (WiMAX Mobile) protocol.
The document US 2005 0216819 describes a method and a device for encoding and decoding serial turbo-like codes generated by the serial concatenation of external coding, interleaving, parity coding, and internal coding.
The document “A New Class of Turbo-like Codes with Universally Good Performance and High-Speed Decoding” (IEEE Milcom 2005, October 2005), Keith M. Chugg et al., describes a new class of codes known as S-SCP (systematic and serial concatenated parity) codes and in particular F-LDPC (flexible LDPC) codes for which the parity check matrix H can be written in the following form:
                    H        ≡                  (                                                    S                                            V                                            0                                                                    0                                            I                                            G                                              )                                    (        1        )            where I is an identity matrix, G and S are bidiagonal matrices, and V is the product of three matrices according to the IEEE 802.11-04/0953r4 standardization document, K. Chugg et al. (802.11 Task Group N, September 2004). The form of this matrix V imposes a limitation on the encoding and decoding bit rate.
FIGS. 1A and 1B respectively represent the structure of a prior art encoder 10 and a prior art decoder 20. In FIG. 1A, the encoder 10 comprises an external coder 3, an interleaver 5, a serial-parallel converter 7, a parity coder 9, and an internal coder 11. The code generated by this encoder 10 is the result of the serial concatenation of codes successively generated by the external coder 3, the parity coder 9, and the internal coder 11.
According to that architecture, an input bit sequence De is first entirely coded by the external coder 3 and then interleaved by the interleaver 5 to form an interleaved data sequence Di. The serial-parallel converter 7 parallelizes the interleaved data sequence Di. The parity coder 9 then performs a parity calculation by effecting the modulo-2 sum of J bits extracted from the output of the serial-parallel converter 7. The data sequence at the output of the parity coder 9 is then coded by the internal coder 11.
The structure of a decoder 20 comprising an external decoder 15, an interleaver/de-interleaver 17, a parity decoder 19, and an internal decoder 21 is shown in FIG. 1B.
The decoder 20 decodes flexible data iteratively. The flexible data corresponding to the systematic portion of the code is used by the external decoder 15 to obtain extrinsic information I1 that is then interleaved by the interleaver 17 to yield information 12 that can be used by the parity decoder 19, which calculates new extrinsic information I3. On the basis of this information I3 and the flexible data I4 corresponding to the redundant portion of the code, the internal decoder 21 calculates a message I5 that is then decoded by the parity decoder 19 to form a message I6 that is sent to the de-interleaver 17. De-interleaving of the message I6 by the de-interleaver 17 to produce a message I7 completes the iteration of the encoding process.
The major drawback of the encoder 10 (respectively decoder 20) is the latency introduced by its serial type architecture, the effect of which is to limit the encoding (respectively decoding) bit rate.
FIGS. 2A and 2B respectively show the scheduling of the various steps of the encoding process and the decoding process performed by the encoder 10 and the decoder 20, respectively.
With standard encoding using serially concatenated codes, each coder of the encoding device 10, i.e. the external coder 3, the parity coder 9 or the internal coder 11, is activated provided that the preceding coder has completed its task.
FIG. 2A represents very diagrammatically the scheduling in time (abscissa axis) of tasks (ordinate axis) constituting the encoding process executed by the encoder 10, these tasks being carried out successively by the external coder 3, the parity coder 9, and the internal coder 11 from FIG. 1A.
With such scheduling, a first coding step E10 is carried out by the external coder 3 for a time T10. When the step E10 has completely finished, the parity coder 9 executes a calculation step E30 for a time T30. When the step E30 has finished, it is followed by a coding step E50 carried out by the internal coder 11 for a time T50. The time needed to encode a sequence of bits at the input of the encoder 10 is therefore equal to the sum T10+T30+T50. This way of scheduling tasks therefore limits the encoding bit rate of the encoder 10.
FIG. 2B represents a distribution in time (abscissa axis) of decoding tasks (ordinate axis) performed by the decoder 20 from FIG. 1B during one iteration of the process.
According to FIG. 2B, the external decoder 15 executes a decoding step E70 for a time T70. When the step E70 has finished, the parity decoder 19 executes a calculation step E90 for a time T90. Once the step E70 has finished, the internal decoder 21 executes a step E110 for a time T110. The parity decoder 19 then executes a step E130 for a time T130. Thus the duration T of one iteration of the decoding process is equal to the sum of the durations of each of the above steps E70, E90, E110, E130, i.e. T=T70+T90+T110+T130.
The bit rates of the encoding and decoding processes described above are limited because of how the various tasks constituting the encoding and decoding processes are scheduled.
Moreover, the hardware resources of the encoder 10 and the decoder 20 are not used optimally, in the sense that each processing function is not used continuously in the coder 10 or the decoder 20.